Sensor and detector development

Many measurements at the FCC-ee will rely on precisely determining the vertices, measured by dedicated vertex detectors. All vertex detector designs for FCC-ee foresee the use of Monolithic Active Pixel Sensors (MAPS). MAPS combine the generation, amplification, and readout of particle signals in a single piece of silicon. This minimizes power consumption and allows for very light sensors – an important requirement by FCC-ee.

Our group is investigating MAPS produced in the 65 nm TPSCo CMOS process for use in the FCC-ee vertex detectors. Using a 65 nm process enables more logic per area and therefore smaller pixels, a lower power consumption and the construction of very large sensor using the stitching method.

We are characterising the performance of two MAPS prototypes produced in 65 nm: the Analogue Pixel Test Structure (APTS) and Circuit Exploratoire 65 (CE-65). Through radioactive source lab measurements and particle beams at CERN and DESY (test beams), we are evaluating the charge collection properties, hit efficiency and spatial resolution of these sensors and will evolve them to fulfill and go beyond current FCC-ee vertex requirements.

We furthermore simulate the current vertex detector design for the IDEA detector concept in full simulation, which enables the precise study of the vertex detector performance at FCC-ee. Our studies are included in the mid-term report of the FCC Feasibility Study and show that previous assumptions about the crucial material budget of the IDEA vertex detector were reasonable.